Tired of using Dual Core, Core 2 Duo, Core I 3/5/7? How about using a processor that has 100-Core Chips! I’m not joking. Yes, it’s 100-Core Chips! MIT researchers have refined a software-based chip simulator that tests chip designs with large numbers of cores for flaws, adding the ability to measure designs’ potential power consumption, and also processing times for tasks, memory access, and core-to-core communications patterns. This new processor is being targeted for fabrication later this year which might have over 100 cores chips.
The name of this new simulator is ‘Hornet.’ When flaws are found, Hornet allows designers to quickly try alternative designs to work around them. Other simulators do more rapid functionality testing, but they are less accurate in their simulation while processing the cycle of a program running on each chip design.
Srini Devadas, who is a professor of Electrical Engineering and Computer Science Department at MIT and principle investigator on Hornet said, “Hornet is more accurate than a functional simulation in measuring how much time it takes to run a program and how much energy is used. You can use it to come up with an interesting computer architecture and test it. There’s always a tradeoff between speed and accuracy. In a design with 256 cores, a simulation would have to account for all of the processes running on each thread—about a million instructions per thread, with one thread per core. That means running 256 million instructions per cycle to test the design, and the time spent running the test shifts from hours to days. If we were designing systems doing 1000 cores, we would need more computers, and need to run them in parallel.”
It means, cores will end up idling endlessly while waiting for each other to release memory or other resources, hanging onto the ones they’ve locked themselves. By measuring the exact results of each computation cycle in a program, Hornet performs ‘cycle-accurate’ simulation of chip designs with up to 1,000 cores. For this accuracy, the Hornet team won the best paper prize at the Fifth International Symposium on Networks-on-Chip in 2011. This was the first version of the simulator where they showed fatal flaws working in a heavily studied multicore-computing technique that other simulations had missed.
At present, most of the testing of silicon simulator has been done by using designs with 64 cores. If MIT research team becomes successful in testing larger numbers of cores perfectly, then they will design and fabricate a new multicore architecture chip named an ‘execution migration machine.’
Devadas mentioned, “We’ve gotten to the point where we’ve gotten confident in the capabilities of the architecture by using Hornet to test on a 64 core design and beyond. The goal is to build a chip with over 100 cores—possibly as many as 128, though the final number hasn’t been determined yet.
Source : Wired